DCDC Register 0
| PWD_ZCD | power down the zero cross detection function for discontinuous conductor mode |
| DISABLE_AUTO_CLK_SWITCH | Disable automatic clock switch from internal osc to xtal clock. |
| SEL_CLK | select 24 MHz Crystal clock for DCDC, when dcdc_disable_auto_clk_switch is set. |
| PWD_OSC_INT | Power down internal osc. Only set this bit, when 24 MHz crystal osc is available |
| PWD_CUR_SNS_CMP | The power down signal of the current detector. |
| CUR_SNS_THRSH | Set the threshold of current detector, if the peak current of the inductor exceeds the threshold, the current detector will assert |
| PWD_OVERCUR_DET | power down overcurrent detection comparator |
| OVERCUR_TRIG_ADJ | The threshold of over current detection in run mode and power save mode: run mode power save mode 0x0 1 A 0 |
| PWD_CMP_BATT_DET | set to “1” to power down the low voltage detection comparator |
| ADJ_POSLIMIT_BUCK | adjust value to poslimit_buck register |
| EN_LP_OVERLOAD_SNS | enable the overload detection in power save mode, if current is larger than the overloading threshold (typical value is 50 mA), DCDC will switch to the run mode automatically |
| PWD_HIGH_VOLT_DET | power down overvoltage detection comparator |
| LP_OVERLOAD_THRSH | the threshold of the counting number of charging times during the period that lp_overload_freq_sel sets in power save mode |
| LP_OVERLOAD_FREQ_SEL | the period of counting the charging times in power save mode 0: eight 32k cycle 1: sixteen 32k cycle |
| LP_HIGH_HYS | Adjust hysteretic value in low power from 12.5mV to 25mV |
| PWD_CMP_OFFSET | power down output range comparator |
| XTALOK_DISABLE | 1’b1: Disable xtalok detection circuit 1’b0: Enable xtalok detection circuit |
| CURRENT_ALERT_RESET | reset current alert signal |
| XTAL_24M_OK | set to 1 to switch internal ring osc to xtal 24M |
| STS_DC_OK | Status register to indicate DCDC status. 1’b1: DCDC already settled 1’b0: DCDC is settling |